In general, in a semiconductor integrated circuit that processes input data synchronously with clock signal, it is necessary for the internal flip-flop circuits or other memory elements to keep the input data at the high level or the low level during the period around the time when the input data are input. If the input data changes during that period, the data input to the memory elements become unstable, and the normal circuit operation cannot take place.
The time of confirming the input data before they are input is known as the setup time, and the time of holding the input data after the input is known as the hold time.
FIG. 12 shows an example of a checking device used for checking the setup time and the hold time of an LSI.
In checked LSI 3, checking data DAT and clock signal CLK are supplied from LSI tester 1 via timing adjustment circuit 2. Timing adjustment circuit 2 precisely adjusts the phase relationship between data DAT and clock signal CLK corresponding to a control signal CNT supplied from LSI tester 1. Timing adjustment circuit 2 is arranged close to semiconductor integrated circuit 3 so that the delay occurring in the signal path between LSI tester 1 and checked LSI 3 will not generate errors during the test.
LSI tester 1 checks the response of checked LSI 3 while the phase relationship between data DAT and clock signal CLK is being precisely adjusted to determine whether the setup time and the hold time of checked circuit LSI 3 satisfy prescribed specifications.
On the other hand, the operating speed of semiconductor integrated circuits have steadily increased. For example, in the high-speed differential transmission system known as LVDS (low voltage differential signaling), it is required that the skew of the clock and data signals be restrained to about several hundred psec.
When conducting an AC test on high-speed signals such as LVDS, it is necessary to adjust the timing of the signal with a high resolution, such as 100 psec or lower. However, it is very difficult to guarantee the test accuracy to such a high resolution with current high-speed LSI testers. Even if such a test can be realized, since the test system is easily affected, it is difficult to conduct stable production line tests, etc. Also, since high-speed testers are usually expensive, the manufacturing cost will be increased.
Consequently, the method known as BIST (built-in self test), which conducts the test that was formerly conducted by LSI testers or other external devices with a special circuit inside the semiconductor integrated circuit, has become popular (for example, see patent reference 1). Since the influence of signal delay can be avoided inside the semiconductor integrated, high-speed signals can be processed more accurately than with an external device.
[Patent reference 1] Japanese Kokai Patent Application No. 2002-6003
However, as the signal speed is increased as in LVDS, the delay characteristic tends to vary for each individual circuit due to variations in manufacturing conditions and other factors even if the circuit is inside the semiconductor integrated circuit. Consequently, it is desired to adjust the timing of the input signal used as the object to be inspected over a wide range when checking the setup time and hold time. Also, since the checking circuit built into the semiconductor integrated circuit makes no contribution to the main operation, its configuration should be as simple as possible.
A general object of the present invention is to provide a semiconductor integrated circuit, which can self-check the circuit operation pertaining to the timing relationship between plurality of input signals and can adjust the timing of the input signals used as object to be inspected over a wide range with a simple configuration.